In addition to testing normal read/write storage array structures, memory test systems are used to test read-only memories (ROMs), fuse mappings, non-volatile test result structures, and other components and devices not well suited for algorithmic tests (e.g., tests not well suited for data generated using an algorithm pattern generator). Conventional automated test equipment (ATE) systems typically employ large, interleaved dynamic random access memories (DRAMs) to provide high-speed read or write data for these non-algorithmic components and devices. However, interleaved DRAM test solutions are expensive in terms of cost and complexity.